View AT86RF230-ZU_1218439.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

zigbee?/ieee 802.15.4- transceiver at86rf230 5131a-zigb-06/14/06 features ? fully integrated 2.4 ghz-band transceiver ? -101 dbm receiver sensitivity ? low current consumption (typical values) ? sleep = 0.1 a ? trx_off = 1.7 ma ? rx_on = 16 ma ? busy_tx = 17 ma (max. p tx ) ? power supply range 1.8v ? 3.6v ? internal ldo voltage regulators ? battery monitor ? spi slave interface ? baseband signal processing compliant with ieee 802. 15.4 ? sfd detection, spreading/de-spreading, framing ? 128-byte fifo for trx ? integrated crystal oscillator, 16 mhz ? digital rssi register, 5-bit value ? fast power-up time < 1 msec ? programmable tx output power from -17 dbm up to 3 d bm ? integrated lna ? low external component count ? antenna ? reference crystal ? de-coupling capacitors ? integrated tx/rx switch ? integrated pll loop filter ? automatic vco and filter calibration ? 32-pin low-profile lead-free plastic qfn package 5 mm x 5 mm x 0.9 mm ? compliant to en 300 440/328, fcc-cfr-47 part 15 ? compliant to ieee 802.15.4 applications ? 802.15.4 transceiver ? transceiver for zigbee system solutions description the at86rf230 is a low-power 2.4 ghz transceiver sp ecially designed for low cost zigbee/ieee802.15.4 applications. the at86rf23 0 is a true spi-to- antenna solution. all rf-critical components except the antenna, crystal and de- coupling capacitors are integrated on-chip.
2 at86rf230 5131a-zigb-06/14/06 table of contents 1. abbreviations ...................................... ................................................... ................................................... .......4 2. general circuit description........................ ................................................... ................................................... 5 3. technical parameters............................... ................................................... ................................................... .6 3.1. absolute maximum ratings........................... ................................................... ...........................................6 3.2. recommended operating range........................ ................................................... .....................................6 3.3. digital pin specifications ......................... ................................................... .................................................6 3.4. general rf specifications.......................... ................................................... ..............................................7 3.5. transmitter specifications ......................... ................................................... ...............................................7 3.6. receiver specifications ............................ ................................................... ................................................8 3.7. current consumption specifications ................. ................................................... .......................................9 3.8. spi timing specifications.......................... ................................................... ...............................................9 3.9. crystal parameter specifications ................... ................................................... ........................................10 4. basic operating modes .............................. ................................................... ................................................11 4.1. configuration ...................................... ................................................... ................................................... .11 4.2. basic operating mode description................... ................................................... ......................................12 4.2.1. p_on ............................................... ................................................... ..................................................1 2 4.2.2. sleep.............................................. ................................................... ..................................................1 2 4.2.3. trx_off............................................ ................................................... ...............................................12 4.2.4. pll_on ............................................. ................................................... ................................................12 4.2.5. rx_on and busy_rx .................................. ................................................... ....................................13 4.2.6. rx_on_noclk ........................................ ................................................... ........................................13 4.2.7. busy_tx............................................ ................................................... ...............................................13 4.3. basic mode timing .................................. ................................................... ...............................................13 4.3.1. wake-up procedure .................................. ................................................... .........................................13 4.3.2. transition from pll_on via busy_tx to rx_on........ ................................................... ....................14 4.3.3. state transition timing ............................ ................................................... ..........................................15 5. extended operating modes ........................... ................................................... .............................................16 5.1. peer-to-peer network support ....................... ................................................... ........................................16 5.2. configuration ...................................... ................................................... ................................................... .18 5.3. extended operation mode description ................ ................................................... ..................................18 5.3.1. rx_aack_on ......................................... ................................................... ..........................................18 5.3.2. tx_aret_on......................................... ................................................... ...........................................18 5.3.3. rx_aack_noclk ...................................... ................................................... ......................................19 6. functional description ............................. ................................................... ................................................... 20 6.1. rssi/energy detection .............................. ................................................... ............................................20 6.2. link quality indication ............................ ................................................... ................................................20 6.3. clear channel assessment........................... ................................................... .........................................20 6.4. voltage regulators ................................. ................................................... ................................................20 6.5. battery monitor .................................... ................................................... ................................................... 21 6.6. crystal oscillator ................................. ................................................... ................................................... 22 6.7. pll frequency synthesizer .......................... ................................................... .........................................23 6.8. automatic filter tuning ............................ ................................................... ..............................................24 7. phy to micro-controller interface.................. ................................................... .............................................25 7.1. spi protocol....................................... ................................................... ................................................... ..25 7.2. register access mode (short mode) .................. ................................................... ...................................26 7.3. frame buffer access modes (long modes)............. ................................................... ..............................27 7.4. frame receive procedure ............................ ................................................... .........................................28 7.5. frame transmit procedure ........................... ................................................... .........................................28 7.6. sleep/wake-up and transmit signal.................. ................................................... ....................................29 7.7. interrupt logic.................................... ................................................... ................................................... ..30
3 at86rf230 5131a-zigb-06/14/06 8. control registers .................................. ................................................... ................................................... ...31 9. application circuit ................................ ................................................... ................................................... ....42 10. pin configuration .................................. ................................................... ................................................... ...44 10.1. pin-out diagram.................................... ................................................... ..................................................4 5 10.2. decoupling......................................... ................................................... ................................................... ..45 10.3. analog pins ........................................ ................................................... ................................................... .45 10.4. rf pins............................................ ................................................... ................................................... ....45 10.5. digital pins....................................... ................................................... ................................................... ....46 11. ordering information............................... ................................................... ................................................... .47 12. soldering information.............................. ................................................... ................................................... .47 13. package thermal properties ......................... ................................................... .............................................47 14. package drawing ? 32qn1 ............................ ................................................... ............................................48 15. references......................................... ................................................... ................................................... ......49 16. revisions .......................................... ................................................... ................................................... .......49
4 at86rf230 5131a-zigb-06/14/06 1. abbreviations aack ? auto acknowledge ack ? acknowledge adc ? analog-to-digital converter agc ? automatic gain control aret ? auto retry avreg ? analog voltage regulator batmon ? battery monitor bbp ? base-band processor bpf ? complex band-pass filter cca ? clear channel assessment clkm ? clock main crc ? cyclic redundancy check csma ? carrier sense multiple access dclk ? digital clock dcu ? delay calibration unit dvreg ? digital voltage regulator ed ? energy detection esd ? electro static discharge evm ? error vector magnitude fifo ? first in first out ftn ? automatic filter tuning gpio ? general purpose input output ldo ? low-drop output lna ? low-noise amplifier lo ? local oscillator lqi ? link-quality indication lsb ? least significant bit msb ? most significant bit msk ? minimum shift keying o-qpsk ? offset-quadrature phase shift keying pa ? power amplifier pan ? personal area network per ? packet error rate phy ? physical layer pll ? phase-locked loop por ? power-on reset ppf ? poly-phase filter psdu ? phy service data unit qfn ? quad flat no-lead package rf ? radio frequency rssi ? received signal strength indicator rx ? receiver sfd ? start frame delimiter spi ? serial peripheral interface sram ? static random access memory tx ? transmitter vco ? voltage controlled oscillator vreg ? voltage regulator xosc ? crystal oscillator
5 at86rf230 5131a-zigb-06/14/06 2. general circuit description lna ppf adc agc pa frequency synthesis i q ftn avreg batmon spi slave interface tx power control tx data limiter 5 rssi xosc control logic/ configuration registers clkm xtal1 xtal2 trx data buffer tx bbp rx bbp bpf irq sel sclk miso mosi slp_tr rstn dclk rfp rfn digital domain analog domain dvreg figure 2-1. block diagram of at86rf230 this single-chip rf transceiver provides a complete radio interface between the antenna and the micro- controller. it comprises the analog radio part, digital demodul ation including time and frequency synchronization and data buffering. the number of external components is min imized so that only the antenna, the crystal and fo ur decoupling capacitors are required. the bidirection al differential antenna pins are used in common for rx and tx, so no external antenna switch is needed. the transceiver block diagram is shown in figure 2-1 . the receiver path is based on a low-if topology. the channel filter consists of three single side-band a ctive rc resonators forming a 2 mhz band-pass filte r with a butterworth characteristic centered at 2 mhz. two 1 st -order high-pass filters were added to the signal p ath to achieve capacitive coupling at the single side-band filter (ssbf) output to suppress dc offset and int egrator feedback at the limiter amplifier. the 3-stage limi ter amplifier provides sufficient gain to overcome the dc offset of the succeeding single channel adc and generates a d igital rssi signal with 3 db granularity. the low-i f signal is sampled at 16 mhz with 1-bit resolution and applied to the digital signal processing part. direct vco modulation is used to generate the trans mit signal. the modulation scheme is offset-qpsk (o -qpsk) with half-sine pulse shaping and 32-length block co ding (spreading). this is equivalent to minimum shi ft keying (msk) when transforming the spreading code sequence s appropriately. the modulation signal is applied t o both the vco and the fractional-n pll to ensure the cohe rent phase modulation required for demodulation as an o- qpsk signal. the frequency-modulated lo signal is f ed to the power amplifier. two on-chip low-dropout voltage regulators provide the analog and digital 1.8v supply. the spi interfa ce and the control registers will retain their settings in sle ep mode when the regulators are turned off. the rx and tx signal processing paths are highly integrated and optimize d for low power consumption.
6 at86rf230 5131a-zigb-06/14/06 3. technical parameters 3.1. absolute maximum ratings note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other cond itions beyond those indicated in the operational sections of this specifications is not implied. exposure to absolut e maximum rating conditions for extended periods may affect d evice reliability. no parameter symbol min typ max unit conditions/notes 3.1.1 storage temperature t stor -50 150 c 3.1.2 lead temperature t lead 260 c t = 10s (soldering profile compliant with ipc/jedec j-std-020b) 3.1.3 esd-protection v esd 2 200 500 kv v v compl. to [2], passed 4 kv compl. to [3], compl. to [4], passed 750v 3.1.4 input rf level p rf +10 dbm 3.1.5 voltage on all pins (except pins 13, 14, 29) -0.3 v dd +0.3 3.6 v 3.1.6 voltage on pins 13, 14, 29 -0.3 2 v table 3-1. absolute maximum ratings 3.2. recommended operating range no parameter symbol min typ max unit conditions/notes 3.2.1 operating temperature range t op -40 +85 c 3.2.2 supply voltage v dd 1.8 3.6 v table 3-2. operating range 3.3. digital pin specifications test conditions (unless otherwise stated): t amb = 25c no parameter symbol min typ max unit conditions/notes 3.3.1 high level input voltage v ih v dd ? 0.4 v 3.3.2 low level input voltage v il 0.4 v 3.3.3 high level output voltage v oh v dd ? 0.4 v for all output current loads defined in register trx_ctr_0 3.3.4 low level output voltage v ol 0.4 v for all output current loads defined in register trx_ctr_0
7 at86rf230 5131a-zigb-06/14/06 no parameter symbol min typ max unit conditions/notes 3.3.5 controller clock frequency (clkm) f clkm 0 1 2 4 8 16 mhz mhz mhz mhz mhz mhz programmable in register trx_ctrl_0 table 3-3. digital pin specifications the capacitive load should not be larger than 50 pf for all i/os when using the default driver strengt h settings. generally, large load capacitances will increase th e overall current consumption. 3.4. general rf specifications test conditions (unless otherwise stated): v dd = 3v, f = 2.45 ghz, t amb = 25c, measurement setup see figure 9-1 no parameter symbol min typ max unit conditions/notes 3.4.1 frequency range f 2405 2480 mhz 3.4.2 bit rate f bit 250 kbit/s as specified in [1] 3.4.3 chip rate f chip 2000 kchip/s as specified in [1] 3.4.4 reference oscillator frequency f clk 16 mhz 3.4.5 reference oscillator settling time 0.5 1 ms leaving sleep state to clock available at pin clkm 3.4.6 reference frequency accuracy for correct functionality -60 +60 ppm 40 ppm is required by [1] 3.4.7 20 db bandwidth b 20db 2.8 mhz table 3-4: general rf parameters 3.5. transmitter specifications test conditions (unless otherwise stated): v dd = 3v, f = 2.45 ghz, t amb = 25c, measurement setup see figure 9-1 no parameter symbol min typ max unit conditions/notes 3.5.1 nominal output power p tx 0 3 6 dbm max. value 3.5.2 output power range 20 db 16 steps (register phy_tx_pwr) 3.5.3 output power accuracy 3 db 3.5.4 tx return loss 10 db 100 differential impedance, p tx = 3 dbm 3.5.5 evm 8 %rms channel number = 20 3.5.6 harmonics 2nd harmonic 3rd harmonic -38 -45 dbm dbm
8 at86rf230 5131a-zigb-06/14/06 no parameter symbol min typ max unit conditions/notes 3.5.7 spurious emissions 30 ? 1000 mhz >1 ? 12.75 ghz 1.8 ? 1.9 ghz 5.15 ? 5.3 ghz -36 -30 -47 -47 dbm dbm dbm dbm complies with en 300 440, fcc-cfr-47 part 15, arib std-66, rss-210 table 3-5. tx parameters 3.6. receiver specifications test conditions (unless otherwise stated): v dd = 3v, f = 2.45 ghz, t amb = 25 c, measurement setup see figure 9-1 no parameter symbol min typ max unit conditions/notes 3.6.1 receiver sensitivity -101 dbm awgn channel, per 1%, psdu length of 20 octets 3.6.2 return loss 10 db 100 differential impedance 3.6.3 noise figure nf 6 db 3.6.4 maximum rx input level 10 dbm per 1%, psdu length of 20 octets 3.6.5 adjacent channel rejection -5 mhz 34 dbm per 1%, psdu length of 20 octets, p rf = -82 dbm 3.6.6 adjacent channel rejection +5 mhz 36 dbm per 1%, psdu length of 20 octets, p rf = -82 dbm 3.6.7 alternate adjacent channel rejection -10 mhz 52 dbm per 1%, psdu length of 20 octets, p rf = -82 dbm 3.6.8 alternate adjacent channel rejection +10 mhz 53 dbm per 1%, psdu length of 20 octets, p rf = -82 dbm 3.6.9 spurious emissions lo leakage 30 ? 1000 mhz 1 ? 12.75 ghz -75 -57 -47 dbm dbm dbm 3.6.10 tx/rx carrier frequency offset -300 300 khz sensitivity loss < 2 db 3.6.11 3 rd -order intercept point iip3 -9 db at maximum gain offset freq. interf. 1 = 5 mhz offset freq. interf. 2 = 10 mhz 3.6.12 2 nd -order intercept point iip2 24 db at maximum gain offset freq. interf. 1 = 60 mhz offset freq. interf. 2 = 62 mhz 3.6.13 rssi accuracy absolute -5 5 db tolerance wit hin gain step 3.6.14 rssi dynamic range 84 db 3.6.15 rssi resolution 3 db 3.6.16 minimum rssi value 0 p rf < -91 dbm 3.6.17 maximum rssi value 28 p rf > -10 dbm table 3-6. rx parameters
9 at86rf230 5131a-zigb-06/14/06 3.7. current consumption specifications test conditions (unless otherwise stated): v dd = 3v, t amb = 25c, clkm = off, measurement setup see figure 9-1 no parameter symbol min typ max unit conditions/notes 3.7.1 supply current transmit mode i busy_tx 17 15 13 10 ma ma ma ma p tx = 3 dbm p tx = 1 dbm p tx = -3 dbm p tx = -17 dbm (the current consumption will be reduced by approx. 2 ma at v dd = 1.8v for each output power level) 3.7.2 supply current receive mode i rx_on 16 ma state: rx_on 3.7.3 supply current trx_off mode i trx_off 1.7 ma state: trx_off 3.7.4 supply current sleep mode i sleep 0.1 a state: sleep table 3-7. current consumption 3.8. spi timing specifications test conditions (unless otherwise stated): v dd = 3v, t amb = 25c no parameter symbol min typ max unit conditions/notes 3.8.1 sclk frequency (synchronous) 8 mhz 3.8.2 sclk frequency (asynchronous) 7.5 mhz 3.8.3 sel low to miso active t1 180 ns 3.8.4 sclk to miso out t2 48 ns data hold time 3.8.5 mosi setup time t3 10 ns 3.8.6 mosi hold time t4 10 ns 3.8.7 lsb last byte to msb next byte t5 250 ns 3.8.8 sel high to miso tristate t6 10 ns 3.8.9 slp_tr pulse width t7 65 ns table 3-8. spi timing parameters (see figure 7-2)
10 at86rf230 5131a-zigb-06/14/06 3.9. crystal parameter specifications no parameter symbol min typ max unit conditions/notes 3.9.1 crystal frequency f 0 16 mhz 3.9.2 load capacitance c l 8 14 pf 3.9.3 static capacitance c 0 7 pf 3.9.4 series resistance r 1 100 table 3-9. crystal parameter specifications
11 at86rf230 5131a-zigb-06/14/06 4. basic operating modes this section summarizes all features that are neede d to provide the basic functionality of a transceiv er system, such as receiving and transmitting frames, and powe ring down. these basic operating modes are sufficie nt for zigbee applications and are shown in figure 4-1 . 2 t r x _ o f f s l p _ t r = 1 legend: blue: spi write to register trx_state (0x02) red: control signals via ic pin green: event s l p _ t r = 0 p l l _ o n rx_on pll_on trx_off (clock mode) xosc=on pull=off r x _ o n p_on (power-on after vdd) xosc=on pull=on sleep (sleep mode) xosc=off pull=off (all modes except p_on) force_trx_off (all modes except sleep) frame start frame end frame end busy_tx (transmit mode) pll_on (pll mode) rx_on (rx listen mode) busy_rx (receive mode) clkm=on tx_start slp_tr=1 t r x _ o f f t r x _ o f f 1 3 4 5 7 6 8 9 11 10 rx_on_noclk (rx listen mode) clkm=off s l p _ t r = 1 s l p _ t r = 0 frame start clkm=on rst=0 12 13 figure 4-1. basic operating modes state diagram 4.1. configuration the operating modes are controlled by two signal pi ns and the spi access to register 0x02 (trx_state). the successful state change can be confirmed by reading the transceiver state from register 0x01 (trx_stat us). the pin slp_tr is used to enter sleep mode where cu rrent consumption is minimal (leakage current only) and to wake-up the transceiver. the pin rst provides a reset of all registers and forces the t ransceiver into trx_off mode, if the ic is not in t he p_on mode.
12 at86rf230 5131a-zigb-06/14/06 the state change commands force_trx_off and trx_off both lead to a transition into trx_off state. if the transceiver is in the busy_rx or busy_tx state, the command force_trx_off interrupts the active receiving or transmitting process, and forces an im mediate transition. on the other hand, a trx_off co mmand is stored until a frame currently being received or tr ansmitted is finished. after the end of the frame, the transition to trx_off is performed. 4.2. basic operating mode description 4.2.1. p_on when the external supply voltage (vdd) is first sup plied to the transceiver ic, the system is in the p _on (power- on) mode. in this mode, the crystal oscillator is a ctivated and the master clock for the controller is provided at the clkm pin after a delay of 128s to ensure a steady state of the crystal oscillator. all digital inputs have pull-up or pull-down resist ors (see table 10-3). this is necessary to support controllers where gpio signals are undefined after reset. the input p ull-up and pull-down resistors are disabled when th e transceiver leaves the p_on state. a valid spi write access to the register trx_state with the values trx_off or force_trx_off is necessa ry to leave the p_on state. prior to leaving p_on, the controller must set the pins to the default operating values: slp_tr = 0 an d 1 rst = . an on-chip power-on-reset sets the all register to its default values. a dedicated reset signal from t he controller at the pin rst is not necessary, but recommended for hw/sw synchr onization reasons. 4.2.2. sleep in sleep mode, the entire transceiver ic is disable d. no circuitry is running. the current consumption in this mode is leakage current only. this mode can only be ente red from state trx_off, when the pin slp_tr is set to ?1?. there is no way to switch the transceiver to sleep mode via spi register access. leaving this state is possible in two ways: setting the slp_tr pin to ?0? returns the transceiv er to the trx_off mode without resetting any regist ers. using 0 rst = resets the spi and configuration registers to thei r default values and forces the ic into the trx_off mode. 4.2.3. trx_off the trx_off mode provides the master clock for the controller in synchronous operation mode, allowing the software to run without the need for the radio to b e powered on. the pins slp_tr and rst are enabled for mode control. in this mode, the spi interface and crystal oscilla tor are active. the voltage regulator is enabled an d provides 1.8v to the digital core for have access to the frame da ta buffers. the transition from p_on to trx_off mode is describ ed in section 4.2.1. 4.2.4. pll_on entering the pll_on mode from trx_off will first en able the analog voltage regulator. after the voltag e regulator has settled, the pll frequency synthesizer is enabl ed. when the pll has settled at the receive frequen cy, a successful pll lock is indicated by an interrupt re quest at the irq pin. during pll_on mode, the command rx_on via register 0x02 (trx_state) sets the transceiver to rx_on mode, even if the pll is not yet settled.
13 at86rf230 5131a-zigb-06/14/06 4.2.5. rx_on and busy_rx the rx_on mode enables the analog and digital recei ver blocks and the pll frequency synthesizer. the transition from trx_off mode to rx_on mode is start ed by setting the trx_state to rx_on via a spi writ e access to register 0x02 (trx_state). the receive mode is internally divided into rx_on m ode and busy_rx mode. there is no difference betwee n the modes with respect to the analog radio part. during rx_on mode, only the preamble detection of the dig ital signal processing is running. when a preamble is detected, the digital receiver is turned on, switching to th e busy_rx mode. slp_tr = 1 is only evaluated in rx_on mode. when re ceiving a frame in busy_rx mode, the slp_tr pin has no effect. 4.2.6. rx_on_noclk if the radio is listening for an incoming frame and the controller is not running an application, the controller can be powered down to decrease the total system power con sumption. this special power-down scenario for cont rollers running in synchronous mode is supported by the at8 6rf230 using the state rx_on_noclk. this state can only be entered by setting slp_tr = 1 while the ic is in the rx_on mode. the clkm pin w ill then be disabled 35 clock cycles after the rising edge a t the slp_tr pin. this will enable the controller t o complete its power-down sequence. the reception of a frame is si gnalized to the controller by a rx_start irq (see figure 7-13 ). the clock clkm is turned on once again and the t ransceiver enters the busy_rx state. the end of the transaction is signaled to the contr oller by an trx_end interrupt. after the transactio n has been completed, the transceiver will enter the rx_on sta te. the transceiver will only re-enter the rx_on_no clk state when the slp_tr has been reset to ?0?, and afterwar ds set to ?1? again. if the transceiver is in the rx_on_noclk state, and the slp_tr pin is reset to ?0?, it will enter the rx _on state, and it will again start to supply the micro-control ler with the clock signal. 4.2.7. busy_tx transmitting can only be started from pll_on mode. there are two ways to start transmitting: using pin slp_tr = 1 or spi command tx_start in register 0x02 (trx_state). either of these will cause the ic to enter busy_tx mode. during the transition to busy_tx mode, the pll freq uency shifts 1.5 mhz to enable the different lo fre quencies needed between receive and transmit modes. transmis sion of the first data chip of the preamble is dela yed by 16 s to allow pll settling and pa ramping. when the end of the frame has been transmitted, the ic will automatically turn off the power amplifier and transition from the busy_tx mode to the pll_on mode. the pll s ettles to the receiver lo frequency (-1.5 mhz frequ ency step). if the frame transmission was initiated by setting the pin slp_tr to ?1?, a new transmission will only be started when the pin slp_tr has been reset to ?0? and after wards to set to ?1? again. 4.3. basic mode timing the following paragraphs depict the method of switc hing from one mode to another. 4.3.1. wake-up procedure the wake-up procedure from sleep mode is shown in figure 4-2 . deasserting the pin slp_tr enables the crystal osci llator. after approximately 0.3 - 0.5 ms, the inter nal clock signal is available. after 128 s the clock signal is delivered at the clkm pin providing the master c lock to the
14 at86rf230 5131a-zigb-06/14/06 micro-controller. an additional 256 s timer ensure s that frequency stability is sufficient to drive f ilter tuning (ftn) and the pll. after band-gap voltage and digital vol tage regulator settling, the transceiver enters the trx_off state and waits for further commands. 0 600 500 700 active blocks 800 900 1000 1100 ftn bg dvreg avreg 16 s pll timer 256 s timer 128 s trx_off state pll_on command pll_on, rx_on slp_tr=0 xosc timer 128 s vdd on xosc trx_off typical block settling time, stays on block active waiting for spi commands p_on xosc delivers clock clkm delivers clock clock stable irq pll locked signals/events rx_on rx_on sleep rst=0 pin clkm_ctrl ~400 time [ s] time [ s] ? ? ? ? figure 4-2. wake-up procedure from sleep mode and p_on mode to rx_on mode (pll locked) forcing pll_on mode or rx_on mode initiates a ramp- up sequence of the analog voltage regulator followe d by a 16 s timer. this timer makes sure that the analog 1.8v supply is stabilized before enabling pll circu itry. rx_on mode can be forced any time during pll_on mode rega rdless of the pll lock signal. when the wake-up sequence is started from p_on mode (vdd first applied to the ic) the state machine wi ll stop after the 128 s timer to wait for a valid trx_off command from the micro-controller. the default clkm frequency value in p_on mode is 1 mhz. at this rate , an spi access requires approximately 38 s. the s pi programming in synchronous mode can be speeded up b y setting the frequency of the clock output at pin clkm in register 0x03 (trx_ctrl_0) to the maximum value all owed. if a chip reset with 0 rst = is generated, the sequence starts with filter tuni ng (ftn) as indicated in figure 4-2. 4.3.2. transition from pll_on via busy_tx to rx_on pll timer 14 2 command slp_tr=0 pll settling to tx frequency pa ramp busy_tx pll_on active blocks state 0 10 16 transmitting frame pll_on time [ s] timer 32 pll settling to rx frequency x x+32 pin tx _ start pll rx_on rx_on typical block settling time, stays on block active waiting for spi commands time [ s] s ? s ? s ? figure 4-3. switching from tx to rx the time scale in figure 4-3 is relative to tx frame start.
15 at86rf230 5131a-zigb-06/14/06 4.3.3. state transition timing the transition numbers correspond to figure 4-1 and do not include spi access time if not otherwis e stated. see measurement setup in figure 9-1 . no transition time [ ? s] (typical) comments 1 p_on trx_off 1880 internal power-on reset, including 1000 s for controller access, depends on external block capacitor at vdec1 (1 f no m) and crystal oscillator setup (c l = 10 pf) 2 sleep trx_off 880 depends on external block capacitor at vdec1 (1 f nom) and crystal oscillator setup (c l = 10 pf) 3 trx_off sleep 35 35 cycles of 1 mhz clock assumed. 4 trx_off pll_on 180 depends on external block capacitor at vdec2 (1 f nom). 5 pll_on trx_off 1 6 trx_off rx_on 180 7 rx_on trx_off 1 8 pll_on rx_on 1 9 rx_on pll_on 1 10 pll_on busy_tx 16 asserting slp_tr pin 11 busy_tx pll_on 32 12 all modes trx_off 1 using trx_cmd force_trx_off (see register 0x02), n ot valid for sleep mode 13 0 rst = trx_off 120 depends on external block capacitor at vdec1 (1 f nom), not valid for p_on mode table 4-1. state transition timing the state transition timing is calculated based on the timing of the single blocks shown in figure 4-2 . the worst case values include maximum operating temperature, minimum supply voltage, and device parameter variat ions. block time [ ? s] (typical) time [ ? s] (worst case) comments xosc 500 1000 depends on crystal q factor and load capacitor. dvreg 60 1000 depends on external block capacitor a t vdec1 (cb3 = 1 f nom., 10 f worst case). avreg 60 1000 depends on external block capacitor a t vdec2 (cb1 = 1 f nom., 10 f worst case). pll, initial 100 150 pll, rx tx 16 pll, tx rx 32 table 4-2. block timing
16 at86rf230 5131a-zigb-06/14/06 5. extended operating modes the at86rf230 transceiver implements address filter ing, automatic acknowledgement frame generation and automatic frame retransmission for peer-to-peer net works in compliance with the ieee 802.15.4 standard . automatic modes help to achieve low power consumpti on and low peak current: tx-aret (transmit/auto-ret ry) and rx-aack (receive/auto-acknowledge). a tx-aret transaction consists of: ? csma/ca ? frame transmission (if the channel is available) a nd automatic crc generation ? reception of ack frame (if required by frame type and ack request) ? retry of csma/ca if the channel is busy or an ack is expected but not received ? interrupt signaling at the end of the transaction, with exit code (success, channel busy, no ack) a rx-aack frame reception consists of: ? frame reception and automatic crc check ? address filtering ? interrupt signaling that the frame was received (i f it passes address filtering) ? automatic ack frame transmission (if the received frame passed the address filter and if an ack is required by the frame type and ack request) a state diagram including these extended operating modes is shown in figure 5-1 . 5.1. peer-to-peer network support the automatic modes of the at86rf230 are designed f or peer-to-peer networks and non-slotted operation, as defined in the ieee 802.15.4 standard. note that automatic crc generation can only be appl ied in conjunction with the tx-aret mode, and autom atic crc check will only be applied in rx-aack mode. in rx-aack mode, an ack frame will always be sent w ith the data-pending bit set to zero. in tx-aret mo de, an ack is considered to be valid if the crc is valid, and if the sequence number of the ack corresponds t o the previously transmitted frame. the value of the ?dat a-pending? bit is ignored. important note: ack frames will not be automaticall y generated for frames with either the broadcast pa n id (0xffff) or a broadcast address.
17 at86rf230 5131a-zigb-06/14/06 2 t r x _ o f f s l p _ t r = 1 legend: blue: spi write to register trx_state (0x02) red: control signals via ic pin green: event s l p _ t r = 0 p l l _ o n rx_on pll_on trx_off (clock mode) xosc=on pull=off r x _ o n p_on (power-on after vdd) xosc=on pull=on sleep (sleep mode) xosc=off pull=off (all modes except p_on) force_trx_off (all modes except sleep) frame start frame end frame end busy_tx (transmit mode) pll_on (pll mode) rx_on (rx listen mode) busy_rx (receive mode) clkm=on tx_start slp_tr=1 t r x _ o f f t r x _ o f f 1 3 4 5 7 6 8 9 11 10 rx_on_noclk (rx listen mode) clkm=off s l p _ t r = 1 s lp_tr=0 frame start clkm=on tx_aret_on (auto retry) rx_aack_on (auto acknowledge) busy_rx_aack (auto acknowledge) busy_tx_aret (auto retry) frame start trans- action finished rx_aack_on tx_aret_on tx_aret_on pll_on tx_start slp_tr=1 frame end rx_on rx_aack_on p l l _ o n r x _ a a c k _ o n t x _ a r e t _ o n rx_aack_ on_noclk (auto acknowledge) busy_rx_ aack_noclk (auto acknowledge) frame start frame rejected frame accepted r x _ o n t x _ a r e t _ o n r x _ a r e t _ o n from trx_off from trx_off slp_tr=1 slp_tr=0 rst=0 12 13 figure 5-1. extended operating mode state diagram
18 at86rf230 5131a-zigb-06/14/06 5.2. configuration the initialization of the at86rf230 prior to using rx-aack or the tx-aret mode is similar to initializ ing the ic prior to switching to regular rx or tx modes. rx_aack_on mode is enabled after the register bits trx_cmd in register 0x02 (trx_state) is written usi ng rx_aack_on. the ic is in the rx_aack_on mode when t he register 0x01 (trx_status) changes to rx_aack_on or busy_rx_aack. for correct rx_aack_on operation, the register bit tx_auto_crc_on (register 0x05) must be set to ?1?. similarly, tx_aret_on mode is enabled after the reg ister bits trx_cmd is written with tx_aret_on. the ic is in the tx_aret_on mode after trx_status changes to tx_aret_on or to busy_tx_aret. for correct tx- aret operation, the register bit tx_auto_crc_on (re gister 0x05) must be set to ?1?. the csma/ca algorithm can be configured using the 0 x2d (csma_seed_0) and the 0x2e (csma_seed_1) registers. the min_be register bits sets the minimu m back-off exponent (refer to the ieee 802.15.4 sta ndard), and the csma_seed_* register bits define a random seed for the back-off-time random-number generator in th e at86rf230. the register bits max_csma_retries (regi ster 0x2c) configures how often the transceiver wil l retry the csma/ca algorithm after a busy channel is initially detected. both automatic modes can be exited by writing a new mode command to the register bits trx_cmd in regis ter 0x02 (trx_state). polling the 0x01 (trx_status) reg ister for the new state confirms that the transceiv er has left the automatic mode. 5.3. extended operation mode description 5.3.1. rx_aack_on in the rx_aack_on mode, the transceiver listens for incoming frames. after detecting a frame start, the transceiver will parse the frame contents for frame type and destin ation address. the filtering procedure described in ieee 802.15.4 will be applied to the frame. any frames rejected b y address filtering will be discarded. a frame will also be d iscarded if the crc is found to be invalid. otherwise, the trx_end interrupt will be raised aft er the reception of the frame is completed. the con troller can then upload the frame. the transceiver also detects if an ack frame needs to be sent. if this is true, the transceiver will a utomatically send an ack frame 12 symbol periods after the end of the received frame. only acks with a cleared data-pend ing bit will be transmitted. no ack will be sent if no ack is required. 5.3.2. tx_aret_on in tx_aret_on mode, the transceiver executes the cs ma/ca algorithm and transmits a frame downloaded by the controller. if necessary, it will check for an ack reply, and signal the result of the transaction by raising a trx_end interrupt. after the interrupt, the control ler may read the value of the register bits trac_st atus (register 0x02) to determine whether or not the tra nsaction was successful. the csma/ca transmission transaction is started by pulsing the slp_tr pin high for at least one micros econd. the frame data must have already been downloaded. a lternatively, the controller may download the frame data while the transceiver is transmitting the preamble. in this case, it is the responsibility of the cont roller to ensure that the data arrives sufficiently early. the transceiver executes the un-slotted csma/ca alg orithm as defined by the ieee 802.15.4 standard. if a clear channel is detected during csma/ca execution, the t ransceiver will proceed to transmit the frame. if t he csma/ca did not detect a clear channel, the channel access will be retried as often as set by the register bit s max_csma_retries in register 0x2c (xah_ctrl). in ca se that csma/ca does not detect a clear channel
19 at86rf230 5131a-zigb-06/14/06 even after the maximum number of retries, it will a bort the transaction, raise the trx_end interrupt, and set the value of the trac_status register bits to channel_a ccess_failure. upon the detection of a clear channel, the transcei ver starts the frame transmission. it parses the fr ame as it is transmitted to check if an ack reply will be expect ed. if no ack is expected, the transceiver will rai se an interrupt after the frame transmission completes. the value o f register bits trac_status (register 0x02) is set to success. on the other hand, if the transmitted frame require s an ack, the transceiver switches into receive mod e to wait for a valid ack reply. if no valid ack is received, the transceiver will retry the entire transaction, inc luding csma/ca execution, until the frame has been acknowledged or the maximum number of retransmissions (as set by t he register bits max_frame_retries in register 0x2c) h as been reached. in this case, the trx_end interrup t is raised and the value of trac_status is set to no_ac k. if a valid ack is found, the trx_end interrupt will be raised. in this case, trac_status is set to suc cess. 5.3.3. rx_aack_noclk if the radio is listening for an incoming frame and the controller is not running an application, the controller can be powered down to decrease the total system power con sumption. this special power down scenario (similar to rx_on_noclk) for controllers running in synchronous mode is supported by the at86rf230 using the state rx_aack_noclk. the state can only be entered by setting slp_tr = 1 while the ic is in the rx_aack_on mode. the clkm p in will be disabled 35 clock cycles after the rising e dge at the slp_tr pin. this will enable the control ler to complete its power down sequence. in rx_aack_noclk mode, the transceiver listens for ieee 802.15.4 frames. should the at86rf230 detect a n start-of-frame-delimiter, it will enter the busy_rx _aack_noclk state, and it will start to receive the frame. if the frame passes the address filter, the at86rf230 enters the busy_rx_aack state, and the clock suppli ed to the micro-controller is turned back on. the control ler may now process the incoming frame. if the received frame has a valid crc, and if it re quires an acknowledgement, the transceiver will aut omatically generate and transmit an ack frame. the end of the transaction is signaled to the contr oller by an trx_end interrupt. after the transactio n has been completed, the transceiver will enter the rx_aack_o n state. the transceiver will only re-enter the rx_aack_noclk state when the slp_tr has been reset to ?0?, and afterwards set to ?1? again. if the transceiver is in the rx_aack_noclk state, a nd the slp_tr pin is reset to ?0?, it will enter th e rx_aack_on state, and it will again start to supply the micro-controller with the clock signal.
20 at86rf230 5131a-zigb-06/14/06 6. functional description 6.1. rssi/energy detection the internal limiter amplifier provides an rssi val ue which reflects the current receive signal streng th at the antenna pin of the at86rf230. the rssi is a 5-bit v alue indicating the receive power in steps of 3 db (see register 0x06), and is updated every 2 s. the receiver ed measurement is used with the channe l-scan algorithm. an ed request (write access to re gister 0x07) as defined by the ieee 802.15.4 standard has a measurement time of 128 s. the ed measurement result is accessible after the measurement time at registe r 0x07 (phy_ed_level). with every frame reception ( sfd detection), an ed measurement is automatically star ted. the ed measurement result has the same range a s the rssi value (register 0x06), but with a 1 db resolut ion. 6.2. link quality indication the ieee 802.15.4 standard defines the link quality indication (lqi) measurement as a ?characterizatio n of the strength and/or quality of a received packet?. the lqi measurement of the at86rf230 is implemented as a characterization of both the quality and signal str ength. an average correlation value of multiple sym bols is calculated and appended to each frame after scaling to a value ranging from 0 to 255. the minimum lqi value of 0 is associated with a low signal quality, resulting from high signal distortions, and/or a signal stren gth that is below the receiver sensitivity. the maximum value of 255 is associated with a signal strength higher than th e receiver sensitivity and a high signal quality resulting fro m low signal distortions. signal distortions are ma inly generated by interference and multipath propagation. 6.3. clear channel assessment the ieee 802.15.4 standard defines three clear chan nel assessment (cca) modes: ? mode 1: energy above threshold only ? mode 2: carrier sense only ? mode 3: carrier sense with energy above threshold all three modes are available in at86rf230. the mod es are configurable via register 0x08 (phy_cc_cca). a cca request is initiated by writing to bit 7 in reg ister 0x08 (phy_cc_cca). after the cca evaluation t ime of 128 s, the cca result is accessible at register 0x01 (t rx_status) bits 6 and 7. bit 7 indicates whether th e cca measurement is finished or not, bit 6 indicates a b usy (bit 6 = 0) or clear channel. (bit 6 = 1) the cca modes are further configurable using regist er 0x09 (cca_thres). the 4-bit value cca_cs_thres can be used for fine t uning the sensitivity of the cca carrier sense algo rithm. higher values increase the probability of clear cha nnel detection. the other 4-bit value (cca_ed_thres) of register 0x 09 (cca_thres) defines the received power threshold of the ?energy above threshold? algorithm. any receive d power above this level will indicate a busy chann el. the threshold is calculated by -91+2cca_ed_thres [dbm] , resulting in a range of -91 dbm to -61 dbm. 6.4. voltage regulators two identical low-dropout voltage regulators are in tegrated within the at86rf230. the avreg provides t he regulated 1.8v supply voltage for the analog sectio n and the dvreg supplies the low-voltage digital se ction. a simplified schematic is shown in figure 6-1 . the voltage regulators are connected internally t o the external unregulated supply voltage vdd. the regulated outpu t voltage is available on pin vdec1 or vdec2. exter nal decoupling capacitors should be connected to these pins to stabilize the regulated supply voltage. a d ecoupling capacitor value of 1 f is recommended for stable operation of the voltag e regulators (see chapter 9), but it can
21 at86rf230 5131a-zigb-06/14/06 range from 400 nf to 10 f. a higher capacitor value provides better voltage stability, but increases the voltage regulator settling time. bandgap voltage reference 1.25v vdec vdd vreg_trim[1:0] figure 6-1. simplified schematic of vreg the voltage regulators can be configured using the register 0x10 (vreg_ctrl). the read-only bit values avdd_ok = 1 and dvdd_ok = 1 indicate a stable, regu lated supply voltage. it is possible to use external voltage regulators i nstead of the internal regulators. for this special application the internal regulators need to be switched off by sett ing the register bits to the values avreg_ext = 1 a nd dvreg_ext = 1. a regulated external supply voltage of 1.8v needs to be connected to the pins vdec1 and vdec2. when turning on the external supply, ensure a sufficiently long stabilization time before inter acting with the at86rf230. 6.5. battery monitor the battery monitor (batmon) detects and signals a low battery or supply voltage. this is done by comp aring the current voltage on the vdd pins with a programmable internal threshold voltage. figure 6-2 shows the simplified schematic of the batmon with the most important inp ut and output signals. batmon_hr batmon_vth 4 vdd threshold voltage batmon_ok ?1? batmon_irq for input-to-output mapping see control register 0x11 (batmon) dac + - d q clear figure 6-2. simplified schematic of batmon
22 at86rf230 5131a-zigb-06/14/06 the batmon can be configured using the register 0x1 1 (batmon). batmon_vth[3:0] sets the threshold voltage. it is programmable with a resolution of 75 mv in the upper voltage range (batmon_hr = 1) and with a resolution of 50 mv in the lower voltage range (bat mon_hr = 0). the signal-bit batmon_ok indicates the current value of the battery voltage: ? if batmon_ok is ?0?, the battery voltage is lower than the threshold voltage ? if batmon_ok is ?1?, the battery voltage is higher than the threshold voltage furthermore, an interrupt (irq7) is automatically g enerated when the battery voltage falls below the p rogrammed threshold (see control register 0x0f and 0x0e). the interrupt appears only when batmon_ok changes from ?1? to ?0?. no interrupt will be generated when: ? the battery voltage is under the default 1.8v thre shold at power up (batmon_ok was never ?1?), or ? a new threshold is set, which is above the current battery voltage (batmon_ok remains ?0?). after setting a new threshold, the value batmon_ok should be read out to verify the current supply vol tage value. when the battery voltage is close to the programmed threshold voltage, noise or temporary voltage drop s can generate a lot of unwanted interrupts initiated by a toggling batmon_ok signal. to avoid this: ? disable the irq7-bit in irq mask register after th e first interrupt and treat the battery as empty, o r ? set a lower threshold value after the first interr upt. note that the battery monitor is inactive during po n and sleep modes, see control register 0x01 (trx_s tatus). 6.6. crystal oscillator the crystal oscillator generates the reference freq uency for the at86rf230. all other internally-gener ated frequencies in the transceiver are derived from thi s unique frequency. therefore the overall system pe rformance is mainly based on the accuracy of this reference freq uency. the external components of the crystal oscil lator should be selected carefully and the related board layout should be done meticulously. the register 0x12 (xosc_ctrl) provides access to th e control signals of the oscillator. basically, two operating modes are supported. a reference frequency can be f ed to the internal circuitry by using an external c lock reference or by setting up the integrated oscillato r as described in figure 6-3 . using the internal oscillator, the oscillation freq uency strongly depends on the load capacitance seen by the crystal between the crystal pins xtal1 and xtal2. the total load capacitance must be equal to the specified lo ad capacitance cl of the crystal itself. it consists o f the external capacitors cx and parasitic capacita nces connected to the xtal nodes. in figure 6-3 , all parasitic capacitances, such as pcb stray cap acitances and the pin input capacitance, are summarized to c par . additional internal trimming capacitors c trim are available. any value in the range from 0 pf to 4.8 pf with a 0.3 pf resolution is selectable using the register bits xtal_trim[3:0 ]. to calculate the total load capacitance, the following formula can be used cl = 0.5*(cx+c trim +c par ). the trimming capacitors provide the possibility of an easy adjustment of frequency changes caused by p roduction process variations or by tolerances of the external components. note that the oscillation frequency ca n be reduced only by increasing the trimming capacitance. the fr equency deviation caused by one unit of c trim decreases with increasing crystal load capacitor values. an amplitude control circuit is included to ensure stable operation with different operating conditio ns and different crystal types. a high current during the amplitude build-up phase guarantees a low start-up time. at s table operation, the current is reduced to the amount nec essary for a robust operation. this also keeps the drive level of the crystal low. generally, crystals with a higher load capacitance are less sensitive to parasitic pulling effects cau sed by external component variations or by variations of board and circuit parasitics. on the other hand, a larger cry stal load capacitance results in a longer start-up time and a higher steady state current consumption.
23 at86rf230 5131a-zigb-06/14/06 cx cx 16mhz xtal1 xtal2 vdd c trim c trim c par c par at86rf230 pcb xtal_trim[3:0] xtal_trim[3:0] figure 6-3. simplified xosc schematic with external components when using an external reference frequency, the sig nal needs to be connected to pin xtal1 as indicated in figure 6-4 and the register bits xtal_mode needs to be set to the external oscillator mode. the oscillation ampl itude shouldn?t be larger than 500 mv, peak-to-peak. xtal1 xtal2 at86rf230 pcb 16 mhz figure 6-4. setup for using an external frequency reference 6.7. pll frequency synthesizer the synthesizer of the at86rf230 is implemented as a fractional-n pll. two calibration loops ensure co rrect functionality within the specified operating limits . the center frequency control loop ensures a correct center frequency of the vco for the currently prog rammed channel. the center frequency calibration algorithm can be started manually by setting pll_cf_start = 1 of register 0x1a (pll_cf). the result of the calibrati on is also available in this register. the delay calibration unit compensates the phase er rors inherent in fractional-n plls. using this tech nique, unwanted spurious frequency components beside the r f carrier are suppressed, and the pll behaves almos t like an integer-n pll. a calibration cycle can be initia ted by setting the register bit pll_dcu_start = 1 o f the register 0x1b (pll_dcu). the calibration result is written to the register bits pll_dcuw.
24 at86rf230 5131a-zigb-06/14/06 both calibration routines will be initiated automat ically when the pll is turned on. additionally, the center frequency calibration is running when the pll is programmed t o a different channel (register 0x08 bits [4:0]). i f the pll is not turned off for a long time, the control loops shoul d be manually initiated from time to time. the cali bration interval depends on environment temperature variations but s hould not be longer than 5 min. 6.8. automatic filter tuning the filter-tuning unit is a separate building block within the at86rf230. a calibration cycle is initi ated automatically when entering the trx_off state from either the sle ep, reset or p_on states. the result of the calibra tion is the 6-bit word ftnv, and is written to the register 0x18 (ftn_ctrl). the filter-tuning value ftnv is used to provide a s table ssbf transfer function and pll loop-filter ti me constant independent of temperature effects and part-to-part variations. it is possible to trigger the calibration algorithm manually by setting the register bit ftn_start = 1 .
25 at86rf230 5131a-zigb-06/14/06 7. phy to micro-controller interface in the following paragraphs, the phy to micro-contr oller interface is defined. the spi protocol and ti ming access are shown, as well as buffer access modes with exam ples. controllers with an spi interface such as an avr wi ll work with the at86rf230 interface. the spi inter face is used for both register programming as well as for f rame transfer. the additional control signals are c onnected to the gpio interface of the controller. figure 7-1 shows the signals which need to be connected betwe en the controller and the transceiver. the clkm signal can be used as a controller main clock (synchronous mo de) or as software timer reference (asynchronous mode). micro-controller at86rf230 mosi miso sclk clkm irq slp_tr mosi miso sclk gpio1/clk gpio2/irq gpio3 mosi miso sclk clkm irq slp_tr gpio4 spi sel sel sel rst rst figure 7-1. phy-host interface 7.1. spi protocol spi is used to program control registers as well as to transfer data frames between the controller and the at86rf230. the additional signals clkm, irq, slp_tr and rst are connected to the gpio interface of the controller. the internal 128-byte frame buffer can keep one tx or one rx frame of maximum length at a time. this o ffers a very flexible data rate over the spi interface. sel sclk miso mosi slp_tr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t7 t4 t2 t1 t5 t6 t3 figure 7-2. spi timing
26 at86rf230 5131a-zigb-06/14/06 the interface is designed to work in synchronous or asynchronous mode. in synchronous mode, the clkm o utput of the transceiver ic is used as the master clock o f the controller. the spi clock can be any integer- divided clock ratio up to 8 mhz. nevertheless, usage of an independent controller cl ock for an asynchronous interface is possible. in a synchronous mode, the maximum spi clock speed is limited to 7.5 mhz. the external clkm output signal is not requir ed and can be disabled. sel enables the miso output driver of the at86rf230. i f the driver is disabled, there is no internal pull -up resistor connected to it. driving the appropriate s ignal level must be ensured by the master device or an external pull-up resistor. the spi is a byte-oriented serial interface. all by tes are transferred msb first. every spi transfer s tarts with 0 sel = and this signal is asserted low as long as one con secutive spi access occurs. one consecutive access includes two or more bytes depending on the access mode described later. if 0 sel = goes high before the end of one complete access, the internal bit counter is re set and the transferred data are lost. both sides of the interface (master and slave) cont ain an 8-bit shift register. the master starts the transfer by asserting 0 sel = . after the 8-bit shift register is loaded, the mas ter generates eight spi clocks in order to transfer the data to the slave, and at the same time the sla ve transmits one byte to the master shift register. if the master wants to receive one byte of data it must also tran smit one byte to the slave. every transfer starts w ith a command byte. this command byte contains the access mode in formation as well as additional mode-dependent bits . during command byte transfer, the at86rf230 returns a byte containing ?0?. bit 7 bit 6 (r/w) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode 1 0 register address [5:0] short mode (register rea d access) 1 1 register address [5:0] short mode (register wri te access) 0 0 1 reserved frame receive mode 0 1 1 reserved frame transmit mode 0 0 0 reserved sram read access mode 0 1 0 reserved sram write access mode table 7-1. interface access mode overview 7.2. register access mode (short mode) the register access mode is a two-byte read/write o peration. the first byte contains the control infor mation (mode identifier bit 7, read/write select bit 6, and a 6- bit address). the second byte contains the read or write data. in this mode a maximum of 64 consecutive registers can be a ddressed. byte 2 byte 1 address[5:0] data[7:0] r/w 1=write 0=read 1 figure 7-3. register short mode access
27 at86rf230 5131a-zigb-06/14/06 clkm sel sclk mosi miso command write data command xx xx xx xx read data write register access read register access figure 7-4. spi register access sequence 7.3. frame buffer access modes (long modes) these modes are used to upload or download frames a s well as access the frame buffer directly. each tr ansfer starts with a control byte. if this byte indicates a frame upload or download, the next byte indicates the frame length followed by the psdu data. in receive mode, after t he psdu data has been received, one more byte is at tached, containing lqi information. the number of bytes for one frame access must be ca lculated by the controller as follows: transmit: byte_count = command byte + frame length byte + fr ame length receive: byte_count = command byte + frame length byte + fr ame length + lqi byte that means there is a maximum frame buffer access o f 129 bytes for tx and 130 bytes for rx. byte 3 byte n byte n-1 byte 2 byte 1 control[4:0] (reserved) frame_length[7:0] tx/rx 0 0 data[7:0] data[7:0] 1 lqi[7:0] figure 7-5. frame receive mode byte 3 byte n byte 2 byte 1 control[4:0] (reserved) frame_length[7:0] tx/rx 1 0 data[7:0] data[7:0] 1 figure 7-6. frame transmit mode if the control byte indicates sram access mode, the next byte contains the start address. as long as sel is low, every subsequent byte read or write increments the address counter of the frame buffer. byte 1 byte 2 byte 3 byte n control[4:0] (reserved) address[7:0] r/w 1=write 0=read 0 data[7:0] data[7:0] 0 figure 7-7. sram access mode
28 at86rf230 5131a-zigb-06/14/06 7.4. frame receive procedure the following transactions are required to receive a frame over the spi: irq issued read irq status register (register access) irq line deasserted receiving frame data (frame receive mode) phy controller figure 7-8. receive frame transactions between at86rf230 and c ontroller clkm sel sclk mosi miso irq slp_tr command xx command xx xx xx xx xx xx xx read data xx frame length frame data 1 frame data 2 frame data 3 frame data n lqi value irq issued irq_status_read frame_upload figure 7-9. frame receive sequence 7.5. frame transmit procedure the following transactions are required to transmit a frame over spi: write frame data to transceiver (frame transmit mod e) write tx_start bit to register (register access) o r assert slp_tr (depends on configuration) phy controller figure 7-10. transmit frame transactions between at86rf230 and controller
29 at86rf230 5131a-zigb-06/14/06 clkm sel sclk mosi miso irq slp_tr command frame length frame data 1 frame data 2 frame data 3 frame data n xx xx xx xx xx xx frame_download transmit start figure 7-11. frame transmit sequence (slp_tr assertion starts t ransmission) 7.6. sleep/wake-up and transmit signal the slp_tr signal is a multi-functional pin. it can be used as transmit start or as a sleep signal. th e function of the pin depends on the transceiver status. transceiver status pin function description trx_off sleep forces the transceiver into sleep mod e rx_on disable clkm forces the transceiver into rx_o n_noclock state and disables clkm pll_on tx start start frame transmission tx_aret_on tx start start of frame retry rx_aack_on tx start start of frame acknowledge table 7-2. slp_tr multi-functional pin states the pin has no function if the transceiver is in ot her modes. if used as a sleep signal, releasing the pin slp_tr = 0 forces the transceiver into trx_off mode and e nables the main clock. if used as a transmit start signal, the low-to-high edge starts the transmission of a frame stored in the frame buffer. from the application point of view, there are two p ossible power-down scenarios supported by the at86r f230. either both the controller and the at86rf230 are po wered down, or the at86rf230 listens for an incomin g frame and only the controller is powered down. the first power-down scenario is shown in figure 7-12 . the controller forces the at86rf230 to sleep mode by setting slp_tr to ?1? when the transceiver is in tr x_off mode. the main clock at pin clkm will be swit ched off after 35 clock cycles. this enables the controller to complete its power-down routine and prevent dead -lock situations. the at86rf230 will awaken when the cont roller releases the pin slp_tr. this concept provid es the lowest possible power consumption. if an incoming frame is expected and no other appli cation is running on the controller, the controller itself can be powered down without the risk of missing an incomin g frame. this scenario is shown in figure 7-13 . in rx_on state, the clkm pin will switched off after 35 cloc k cycles when the pin slp_tr is set to ?1?. the sta rt of a frame reception will be signaled by an rx_start irq and t he clock will be switched on again.
30 at86rf230 5131a-zigb-06/14/06 clkm slp_tr async timer (controller) elapsed 35 main clock cycles figure 7-12. sleep and wake-up initiated by asynchronous contro ller timer output clkm slp_tr irq transceiver irq issued 35 main clock cycles figure 7-13. wake-up initiated by transceiver interrupt 7.7. interrupt logic the at86rf230 can differentiate between six interru pt events. each interrupt can be enabled or disable d by writing the corresponding bit to the interrupt mask register. all six internal interrupt lines are com bined via logical ?or? to one external interrupt line. internally, ea ch interrupt is stored in a separate bit of the int errupt status register. if the external interrupt line is set, th e controller must first read the interrupt status r egister to determine the source of the interrupt. a read access to this regi ster clears the interrupt status register and also the external interrupt line. the interrupt will not be cleared a utomatically when the event that caused the irq is not valid anymore. exception: the pll_lock irq will clear the pll_unlock irq and vice versa. for a detailed description of the interrupt status register, please refer to register 0x0f (irq_status ). note: after a reset signal, all interrupts are enab led. special settings in the register 0x0e (irq_mas k) need to be renewed.
31 at86rf230 5131a-zigb-06/14/06 8. control registers the at86rf230 provides a register space of 64 8-bit registers, which is used to configure the ic as we ll as to store signaling information read by the firmware. note that all registers not mentioned within the fo llowing table are reserved for internal use and mus t not be written to. when writing to a non-reserved register, any in dividual bits of that register marked as reserved c an only be overwritten by their reset value. reg.-addr. register name description 0x01 trx_status transceiver status, cca result 0x02 trx_state state/mode control 0x03 trx_ctrl_0 driver current and controller clock setting 0x05 phy_tx_pwr tx power setting 0x06 phy_rssi rssi value 0x07 phy_ed_level rx energy level 0x08 phy_cc_cca cca mode configuration, cca request , channel setting 0x09 cca_thres cca_ed and cca_cs threshold 0x0e irq_mask interrupt mask 0x0f irq_status interrupt status 0x10 vreg_ctrl voltage regulator control 0x11 batmon battery monitor control 0x12 xosc_ctrl crystal oscillator control 0x18 ftn_ctrl filter tuning control 0x1a pll_cf pll center frequency calibration 0x1b pll_dcu pll delay calibration 0x1c part_num part id 0x1d version_num version id 0x1e man_id_0 manufacturer id, lower 8 bits 0x1f man_id_1 manufacturer id, higher 8 bits 0x20 short_addr_0 short address for address recogni tion 0x21 short_addr_1 short address for address recogni tion 0x22 pan_id_0 pan address for address recognition 0x23 pan_id_1 pan address for address recognition 0x24 ieee_addr_0 current node ieee address for addr ess recognition 0x25 ieee_addr_1 current node ieee address for addr ess recognition 0x26 ieee_addr_2 current node ieee address for addr ess recognition 0x27 ieee_addr_3 current node ieee address for addr ess recognition 0x28 ieee_addr_4 current node ieee address for addr ess recognition
32 at86rf230 5131a-zigb-06/14/06 reg.-addr. register name description 0x29 ieee_addr_5 current node ieee address for addr ess recognition 0x2a ieee_addr_6 current node ieee address for addr ess recognition 0x2b ieee_addr_7 current node ieee address for addr ess recognition 0x2c xah_ctrl retries value control 0x2d csma_seed_0 csma seed value 0x2e csma_seed_1 csma seed value table 8-1. configuration registers overview bit field name reset r/w comments 7 cca_done 0 r 1?d0: cca calculation in progress 1?d1: cca calculation done 6 cca_status 0 r indicates an idle channel from cca module. channel_idle: 1?d0: channel is busy 1?d1: channel is idle 5 0 r reserved 4:0 trx_status 0 r signals the current transceiver status. transceiver_status: 5?d0: p_on 5?d1: busy_rx 5?d2: busy_tx 5?d6: rx_on 5?d8: trx_off (clk mode) 5?d9: pll_on (tx_on) 5?d15: sleep 5?d17: busy_rx_aack 5?d18: busy_tx_aret 5?d22: rx_aack_on 5?d25: tx_aret_on 5?d28: rx_on_noclk 5?d29: rx_aack_on_noclk 5?d30: busy_rx_aack_noclk 5?d31: state transition table 8-2. 0x01 - trx_status note: a register read will reset the cca_status bit and the cca_done bit if a cca calculation was done (cca_done = 1).
33 at86rf230 5131a-zigb-06/14/06 bit field name reset r/w comments 7:5 trac_status 0 r 3?d0: success 3?d3: channel_access_failure 3?d5: no_ack all other values are reserved. 4:0 trx_cmd 0 r/w transceiver control commands: 5?d0: nop 5?d2: tx_start 5?d3: force_trx_off 5?d6: rx_on 5?d8: trx_off (clk mode) 5?d9: pll_on (tx_on) 5?d22: rx_aack_on 5?d25: tx_aret_on all other values are mapped to nop. table 8-3. 0x02 - trx_state note: trx_cmd = ?0? after power on reset (por). frame transmission starts 16 s after tx_start command. bit field name reset r/w comments 7:6 pad_io 0 r/w set the output driver current of d igital pads (except clkm pad). 2?d0: 2 ma 2?d1: 4 ma 2?d2: 6 ma 2?d3: 8 ma 5:4 pad_io_clkm 1 r/w set the output driver current of clkm. 2?d0: 2 ma 2?d1: 4 ma 2?d2: 6 ma 2?d3: 8 ma 3 clkm_sha_sel 1 r/w shadow the clkm_ctrl clock cha nges. if the mode is enabled, changes to the clkm_ctrl bits take effect only when the ic leaves the sleep mode. 1?d0: disable (on the fly) 1?d1: enable (shadow) 2:0 clkm_ctrl 1 r/w controls the clock frequency at the clkm pad. 3?d0: no clock 3?d1: 1 mhz 3?d2: 2 mhz 3?d3: 4 mhz 3?d4: 8 mhz 3?d5: 16 mhz 3?d6: no clock 3?d7: no clock table 8-4. 0x03 - trx_ctrl_0
34 at86rf230 5131a-zigb-06/14/06 bit field name reset r/w comments 7 tx_auto_crc_on 0 r/w auto_crc mode: 1?d0: disable 1?d1: enable 6:4 0 r reserved tx power mapping tx power setting output power [dbm] 0 3.0 1 2.6 2 2.1 3 1.6 4 1.1 5 0.5 6 -0.2 7 -1.2 8 -2.2 9 -3.2 10 -4.2 11 -5.2 12 -7.2 13 -9.2 14 -12.2 3:0 tx_pwr 0 r/w 15 -17.2 table 8-5. 0x05 - phy_tx_pwr bit field name reset r/w comments 7:5 0 r reserved 4:0 rssi 0 r 5?d0: rx input level < -91 dbm 5?d27: rx input level > -10 dbm rssi is a linear curve on a logarithmic input power scale (dbm) with a 3 db step width. table 8-6. 0x06 - phy_rssi
35 at86rf230 5131a-zigb-06/14/06 bit field name reset r/w comments 7:0 ed_level 0 r ed level for current channel. the min. ed value (0) indicates receiver power less than or equal to -91 dbm. the range is 84 db with a resolution of 1 db and an absolute accuracy of 5 db. table 8-7. 0x07 - phy_ed_level note: a write access initiates the ed measurement ( ed.request). bit field name reset r/w comments 7 cca_request 0 r/w 1?d1: starts a cca check (cca.r equest) read value always returns with ?0? 6:5 cca_mode 1 r/w cca mode: 2?d0: mode 1, energy above threshold 2?d1: mode 1, energy above threshold 2?d2: mode 2, carrier sense only 2?d3: mode 3, carrier sense with energy above thres hold channel: according to ieee802.15.4 only 11 to 26 are valid. all unused values are reserved. channel mapping channel number frequency [mhz] 11 2405 12 2410 13 2415 14 2420 15 2425 16 2430 17 2435 18 2440 19 2445 20 2450 21 2455 22 2460 23 2465 24 2470 25 2475 4:0 channel 11 r/w 26 2480 table 8-8. 0x08 - phy_cc_cca
36 at86rf230 5131a-zigb-06/14/06 bit field name reset r/w comments 7:4 cca_cs_thres 12 r/w threshold for cca_cs 3:0 cca_ed_thres 7 r/w an ed value above the thresh old signals a busy channel during a cca_ed measurement. table 8-9. 0x09 - cca_thres note: cca_ed_thres: the cca_ed request will indicat e a busy channel, if the measured receive power is above -91 dbm + 2*cca_ed_thres[db]. bit field name reset r/w comments 7:0 irq_mask 255 r/w mask register for irqs. if bit is set to high, then the irq is enabled. if bit is set to low, then the irq is disabled. irq_mask[7] corresponds to irq_7. irq_mask[0] corresponds to irq_0. table 8-10. 0x0e - irq_mask note: the occurrence of an interrupt will be signal ed over the irq wire. bit field name reset r/w comments 7 irq_7 0 r bat_low: signals low battery 6 irq_6 0 r trx_ur: signals a fifo underrun 5 irq_5 0 r reserved 4 irq_4 0 r reserved 3 irq_3 0 r trx_end: signals end of frame (transmit and receive) 2 irq_2 0 r rx_start: signals beginning of receive frame 1 irq_1 0 r pll_unlock: pll goes from lock to unloc k state 0 irq_0 0 r pll_lock: pll goes from unlock to lock state table 8-11. 0x0f - irq_status note: the occurrence of an interrupt will be signal ed over the irq wire. a read access will reset the interrupt bits. bit field name reset r/w comments 7 avreg_ext 0 r/w 1?d0: use internal analog voltage regulator 1?d1: use external voltage regulator 6 avdd_ok 0 r 1?d0: analog voltage regulator is dis abled 1?d1: internal analog voltage is correct and stable 5:4 avreg_trim 0 r/w controls the voltage of the an alog voltage regulator. 2?d0: 1.80v 2?d1: 1.75v 2?d2: 1.84v 2?d3: 1.88v
37 at86rf230 5131a-zigb-06/14/06 bit field name reset r/w comments 3 dvreg_ext 0 r/w 1?d0: use internal digital voltag e regulator 1?d1: use external voltage regulator 2 dvdd_ok 0 r 1?d0: digital voltage regulator is di sabled 1?d1: internal digital voltage is correct and stabl e 1:0 dvreg_trim 0 r/w controls the voltage of the di gital voltage regulator. 2?d0: 1.80v 2?d1: 1.75v 2?d2: 1.84v 2?d3: 1.88v table 8-12. 0x10 - vreg_ctrl bit field name reset r/w comments 7:6 0 r reserved 5 batmon_ok 0 r result of battery monitor: 1?d0: not valid (vdd < batmon_vth) 1?d1: valid (vdd > batmon_vth) 4 batmon_hr 0 r/w high range switch (mapping see ba tmon_vth) threshold voltage: batmon_vth mapping value voltage [v] batmon_hr = ?1? voltage [v] batmon_hr = ?0? 0 2.550 1.70 1 2.625 1.75 2 2.700 1.80 3 2.775 1.85 4 2.850 1.90 5 2.925 1.95 6 3.000 2.00 7 3.075 2.05 8 3.150 2.10 9 3.225 2.15 10 3.300 2.20 11 3.375 2.25 12 3.450 2.30 13 3.525 2.35 14 3.600 2.40 3:0 batmon_vth 2 r/w 15 3.675 2.45 table 8-13. 0x11 - batmon
38 at86rf230 5131a-zigb-06/14/06 bit field name reset r/w comments 7:4 xtal_mode 15 r/w xtal modes: 4?d0: switch off 4?d4: external oscillator 4?d15: internal oscillator all other modes are reserved and should not be used . 3:0 xtal_trim 0 r/w binary coded capacitance array for xtal trimming. values: 0 pf, 0.3 pf, ?, 4.8 pf table 8-14. 0x12 - xosc_ctrl bit field name reset r/w comments 7 ftn_start 0 r/w 1?d1: initiates filter calibratio n cycle if filter calibration is finished, read value is ?0 ? 6 1 r/w reserved 5:0 ftnv 24 r/w filter tuning value table 8-15. 0x18 - ftn_ctrl bit field name reset r/w comments 7 pll_cf_start 0 r/w 1?d1: initiates pll center fre quency calibration cycle if frequency calibration is finished, read value is ?0? 6:4 5 r/w reserved 3:0 pll_cf 15 r/w vco center frequency control word table 8-16. 0x1a ? pll_cf bit field name reset r/w comments 7 pll_dcu_start 0 r/w 1?d1: initiates pll delay cel l calibration cycle if delay cell calibration is finished, read value i s ?0? 6 0 r reserved 5:0 pll_dcuw 32 r/w delay cell control word table 8-17. 0x1b ? pll_dcu bit field name reset r/w comments 7:0 part_num 2 r the device part number. 8?d2: at86rf230 all other values are reserved table 8-18. 0x1c - part_num bit field name reset r/w comments 7:0 version_num 1 r the device version number. table 8-19. 0x1d - version_num
39 at86rf230 5131a-zigb-06/14/06 bit field name reset r/w comments 7:0 man_id_0 31 r jedec manufacturer id is 32?h 00_ 00_00_1f for atmel, bits[7:0] table 8-20. 0x1e - man_id_0 bit field name reset r/w comments 7:0 man_id_1 0 r jedec manufacturer id is 32?h 00_0 0_00_1f for atmel, bits[15:8] table 8-21. 0x1f - man_id_1 bit field name reset r/w comments 7:0 short_addr_0 0 r/w lower 8 bits of short addres s for address recognition, bits[7:0] table 8-22. 0x20 - short_addr_0 bit field name reset r/w comments 7:0 short_addr_1 0 r/w higher 8 bits of short addre ss for address recognition, bits[15:8] table 8-23. 0x21 - short_addr_1 bit field name reset r/w comments 7:0 pan_id_0 0 r/w lower 8 bits of pan address for address recognition, bits[7:0] table 8-24. 0x22 - pan_id_0 bit field name reset r/w comments 7:0 pan_id_1 0 r/w higher 8 bits of pan address for address recognition, bits[15:8] table 8-25. 0x23 - pan_id_1 bit field name reset r/w comments 7:0 ieee_addr_0 0 r/w lower 8 bits of ieee address for address recognition, bits[7:0] table 8-26. 0x24 - ieee_addr_0 bit field name reset r/w comments 7:0 ieee_addr_1 0 r/w 8 bits of ieee address for ad dress recognition, bits[15:8] table 8-27. 0x25 - ieee_addr_1 bit field name reset r/w comments 7:0 ieee_addr_2 0 r/w 8 bits of ieee address for ad dress recognition, bits[23:16] table 8-28. 0x26 - ieee_addr_2
40 at86rf230 5131a-zigb-06/14/06 bit field name reset r/w comments 7:0 ieee_addr_3 0 r/w 8 bits of ieee address for ad dress recognition, bits[31:24] table 8-29. 0x27 - ieee_addr_3 bit field name reset r/w comments 7:0 ieee_addr_4 0 r/w 8 bits of ieee address for ad dress recognition, bits[39:32] table 8-30. 0x28 - ieee_addr_4 bit field name reset r/w comments 7:0 ieee_addr_5 0 r/w 8 bits of ieee address for ad dress recognition, bits[47:40] table 8-31. 0x29 - ieee_addr_5 bit field name reset r/w comments 7:0 ieee_addr_6 0 r/w 8 bits of ieee address for ad dress recognition, bits[55:48] table 8-32. 0x2a - ieee_addr_6 bit field name reset r/w comments 7:0 ieee_addr_7 0 r/w higher 8 bits of ieee address for address recognition, bits[63:56] table 8-33. 0x2b - ieee_addr_7 bit field name reset r/w comments 7:4 max_frame_retries 3 r/w number of retransmissio n attempts in aret mode before the transaction gets cancelled. 3:1 max_csma_retries 4 r/w number of retries in are t mode to repeat the csma/ca procedures before the aret procedure gives up. 0 0 r/w reserved table 8-34. 0x2c - xah_ctrl bit field name reset r/w comments 7:0 csma_seed_0 234 r/w lower 8 bits of csma_seed, bits[7:0] seed for the random number generator in the csma/ca algorithm table 8-35. 0x2d - csma_seed_0
41 at86rf230 5131a-zigb-06/14/06 bit field name reset r/w comments 7:6 min_be 3 r/w minimum back-off exponent in the c sma/ca algorithm. 5:4 0 r reserved 3 i_am_coord 0 r/w use for address filtering within aack mode (pan coordinator) 1?d0: disable 1?d1: enable 2:0 csma_seed_1 2 r/w higher 3 bits of csma_seed, b its[10:8] seed for the random number generator in the csma/ca algorithm table 8-36. 0x2e - csma_seed_1
42 at86rf230 5131a-zigb-06/14/06 9. application circuit an application circuit with a single-ended rf conne ctor is shown in figure 9-1 . an smd-balun transforms the 100 differential rf inputs/outputs of the at86rf230 to a 50 single ended rf port. the capacitors c1 and c2 form a dc-block. power supply decoupling capacitors (cb2, cb4) are c onnected to the analog (28) and the digital supply pin (15). capacitors cb1 and cb3 are load capacitors for the analog and digital voltage regulators. they ensure a stable operation of the low-voltage parts of the at86rf230 . all decoupling capacitors should be placed as clo se as possible to the at86rf230 pin and need to have a lo w-resistance and low-inductive connection to ground to achieve the best performance. the crystal (xtal), the two load capacitors (cx1, c x2), and the internal circuitry connected to pins x tal1 and xtal2 form the crystal oscillator. to achieve the b est accuracy and stability of the reference frequen cy, large stray capacitances should be avoided. cross coupling of digital signals to the crystal pi ns or the rf pins can degrade system performance. designator description value manufacturer manuf. part number b1 smd balun 2.4 ghz wuerth 748421245 cb1 dc-blocking capacitor 1 f cb2 dc-blocking capacitor 1 f cb3 dc-blocking capacitor 1 f cb4 dc-blocking capacitor 1 f cx1 crystal load capacitor 12 pf cx2 crystal load capacitor 12 pf c1 rf-coupling capacitor 22 pf c2 rf-coupling capacitor 22 pf xtal crystal cx-4025 16 mhz sx-4025 16 mhz acal taitjen siward xwbbpl-f-1 a207-011 table 9-1. bill of materials
43 at86rf230 5131a-zigb-06/14/06 c1 c2 b1 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 25 26 27 28 29 30 31 32 at86rf230 gnd gnd gnd gnd gnd rfp rfn gnd gnd gnd gnd slp_tr gnd vdec1 vdec1 xtal1 vdd gnd gnd vdec2 vdd gnd xtal2 17 18 19 20 21 22 23 24 gnd clkm irq miso gnd mosi sclk cb3 cb4 xtal cx1 cx2 cb1 cb2 rf digital interface v dd rst sel figure 9-1. application schematic
44 at86rf230 5131a-zigb-06/14/06 10. pin configuration number name type description 1 gnd ground analog ground 2 gnd ground analog ground 3 gnd ground ground for rf signals 4 rfp rf i/o differential rf signal 5 rfn rf i/o differential rf signal 6 gnd ground ground for rf signals 7 gnd ground digital ground 8 rst digital input chip reset pin, active low 9 gnd ground digital ground 10 gnd ground digital ground 11 slp_tr digital input controls sleep, transmit an d receive mode, active high 12 gnd ground digital ground 13 vdec1 de-coupling requires de-coupling capacitor 14 vdec1 de-coupling requires de-coupling capacitor 15 vdd supply supply voltage 16 gnd ground digital ground 17 clkm digital output master clock signal output t o drive controller 18 gnd ground digital ground 19 sclk digital input spi clock 20 miso digital output spi data output (master inpu t slave output) 21 gnd ground digital ground 22 mosi digital input spi data input (master output slave input) 23 sel digital input spi select signal, active low 24 irq digital output interrupt request signal 25 xtal1 analog input crystal pin 26 xtal2 analog input crystal pin 27 gnd ground analog ground 28 vdd supply supply voltage 29 vdec2 de-coupling requires de-coupling capacitor 30 gnd ground analog ground 31 gnd ground analog ground 32 gnd ground analog ground table 10-1. at86rf230 pin list
45 at86rf230 5131a-zigb-06/14/06 10.1. pin-out diagram gnd gnd gnd rfp rfn gnd gnd irq mosi gnd miso sclk gnd clkm gnd gnd gnd vdec2 vdd gnd xtal2 xtal1 gnd gnd slp_tr gnd vdec1 vdec1 vdd gnd 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 12 3 4 5 6 7 8 24 23 22 21 20 19 18 17 at86rf230 rst sel 10.2. decoupling correct functionality requires de-coupling of the i nternal power supply voltage (vdec1/2). capacitors of 1f (recommended value) shall be placed as close as pos sible to ic pins and shall be connected to ground w ith the shortest possible traces. avoid long lines. it is r ecommended to insert additional 100 nf capacitors a s close as possible at each vdd pin to ground. 10.3. analog pins pin condition recommendation/comment rfp/rfn v dc = 0.9v (tx) v dc = 20 mv (rx) at both pins blocking is required if an antenna with a dc path t o ground is used. serial capacitance must be < 30 pf. xtal1/xtal2 c par = 3 pf v dc = 0.9v at both pins parasitic capacitance of the ic pins must be consid ered as additional parallel capacitance to the crystal. table 10-2. comments on rf input/output and crystal pins 10.4. rf pins a differential rf input provides common-mode reject ion to suppress the switching noise of the internal digital signal processing blocks. at the board-level, the differen tial rf layout ensures the receiver sensitivity by rejecting any spurious signals originating from other digital ics such as the micro-controller. the rf port is designed for a 100 differential load. a differential dc path between the rf pins is allowed. a dc path to ground or supply voltage is not allowed and requires capacitive coupling as indicated in table 10-2.
46 at86rf230 5131a-zigb-06/14/06 lna pa rfp rfn rxtx 0.9v tx rx cm feedback m0 figure 10-1. simplified rf front-end schematic a simplified schematic of the rf front end is shown in figure 10-1 . rf port dc values depend on the operating mode. in trx_off mode, the rf pins are pulled to gr ound, preventing a floating voltage larger than 1.8 v which is not allowed for the internal circuitry. in receive mode, the rf input provides a low-impedance path to ground when transistor m0 pulls the inductor center tap to grou nd. a dc voltage drop of 20 mv across the on-chip i nductor can be measured at the rf pins. in transmit mode, a reg ulation loop provides a common-mode voltage of 0.9v . transistor m0 is off, allowing the pa to set the co mmon-mode voltage. the common-mode capacitance at e ach pin to ground is limited to < 30 pf to ensure the stabi lity of this common-mode feedback loop. 10.5. digital pins pulling resistors are connected to all digital inpu t pins in transceiver state p_on. table 10-3 summar izes the pull- up and pull-down configuration. in all other states there is no pull-up or pull-dow n resistor connected to any of the digital input pi ns. pin h = pull-up, l = pull-down rst h sel h sclk l mosi l slp_tr l table 10-3. pull-up / pull-down configuration of digital input pins
47 at86rf230 5131a-zigb-06/14/06 11. ordering information ordering code package voltage range temperature range AT86RF230-ZU qn 1.8 ? 3.6v industrial (-40c to 85 c) lead-free/halogen-free package type description qn 32qn1, 32-lead 5.0 x5.0mm body, 0.50mm pitch, qu ad flat no-lead package (qfn) sawn note: t&r quantity 2,500. please contact your local atmel sales office for more detailed ordering info rmation and minimum quantities. 12. soldering information recommended soldering profile is specified in ipc/j edec j-std-.020c. 13. package thermal properties thermal resistance velocity [m/s] theta ja [k/w] 0 40.9 1 35.7 2.5 32.0
48 at86rf230 5131a-zigb-06/14/06 14. package drawing ? 32qn1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32qn1 , 32-lead 5.0 x 5.0 mm body, 0.50 mm pitch, quad flat no lead package (qfn) sawn a 32qn1 1/24/06 notes: 1. this drawing is for general information only. refer to jedec drawing mo-220, variation vhhd-1, for proper dimensions, tolerances, datums, etc. 2. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. common dimensions (unit of measure = mm) symbol min nom max note d 5.00 bsc e 5.00 bsc d2 1.25 3.25 e2 1.25 3.25 a 0.80 0.90 1.00 a1 0.0 0.02 0.05 a2 0.0 0.65 1.00 a3 0.20 ref l 0.30 0.40 0.50 e 0.50 bsc b 0.18 0.23 0.30 2 pin 1 corner pin 1 corner side view bottom view top view a3 l b e2 d2 e e d a a1 a2
49 at86rf230 5131a-zigb-06/14/06 15. references [1] ieee std 802.15.4-2003: wireless medium access control (mac) and physical layer (phy) specificatio ns for low-rate wireless personal area networks (lr-wp ans) [2] ansi / esd-stm5.1-2001: esd association standar d test method for electrostatic discharge sensitivi ty testing ? human body model (hbm) [3] eia / jesd22-a115-a: electronic industries asso ciation, electrostatic discharge sensitivity testin g ? machine model (mm) [4] esd-stm5.3.1-1999: esd association standard tes t method for electrostatic discharge sensitivity te sting ? charged device model (cdm) 16. revisions revision date description 1.0 2006-06-14 initial release
5131a-zigb-06/14/06 atmel corporation 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 atmel operations memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature disclaimer: the information in this document is provided in con nection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this docu ment or in connection with the sale of atmel produc ts. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel as sumes no liability whatsoever and disclaims any exp ress, implied or statutory warranty relating to its products includi ng, but not limited to, the implied warranty of mer chantability, fitness for a particular purpose, or non-infringeme nt. in no event shall atmel be liable for any direc t, indirect, consequential, punitive, special or incidental dama ges (including, without limitation, damages for los s of profits, business interruption, or loss of information) arising out o f the use or inability to use this document, even i f atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descrip tions at any time without notice. atmel does not ma ke any commitment to update the information contained here in. unless specifically provided otherwise, atmel p roducts are not suitable for, and shall not be used in, automotive applications. atmel?s products are not i ntended, authorized, or warranted for use as compon ents in applications intended to support or sustain life. ? 2006, atmel corporation . all rights reserved. atmel ? , logo and combinations thereof, everywhere you are ? and others, are registered trademarks or trademarks of atmel corporation or it s subsidiaries. other terms and product names may b e trademarks of others.

▲Up To Search▲

Price & Availability of AT86RF230-ZU

	To Download AT86RF230-ZU Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .